The performance of pipelined analog-to-digital converters (ADCs) is often limited by inter-stage gain errors and non-linearity. Gain errors can be caused by various factors, including mismatches in the capacitors in any particular stage and limitations in the gain producing capability of amplifiers inside the stage (amplifiers have finite gain). Gain error introduced in one stage tends to propagate through to subsequent stages in the pipeline, resulting in inter-stage gain error that can adversely affect the accuracy and linearity of the ADC output (i.e., the overall linearity of the ADC). Non-linearity of the amplifier can further degrade the overall linearity and refers to when the output of the amplifier is no longer a linear function of the input.
The background section of U.S. Pat. No. 7,786,910 (“the '910 patent,” the content of which is hereby incorporated by reference in its entirety) describes various calibration techniques for gain error correction. In these and other conventional calibration techniques, a random or pseudo-random signal (referred to as dither) is injected in a component of a stage—in particular, injected into a multiplying digital-to-analog-converter (MDAC). The dither sees the same error as the main input signal and therefore the error in the dither detected in the output is indicative of the error experienced by the input signal. Since the dither is uncorrelated with the input signal, it can be separated digitally (by correlating it out) from the output. This is usually done with a digital correlator or using the least means square (LMS) algorithm. Further, by comparing the separated dither with its ideal value, it is possible to estimate the gain error that was encountered as the dither progressed from its point of injection through to the output of the ADC.
One disadvantage of the conventional calibration techniques is that the dither signal consumes a significant portion of the dynamic range of the DACs in each stage of the ADC that the dither propagates through. To overcome this disadvantage, the '910 patent proposes to use a relatively small (low amplitude) dither signal. An injection network with multiple parallel capacitive branches (formed using small capacitors) is used to generate the dither. When the dither is injected, fewer than all of the branches are used. This reduces the amplitude of the dither, thereby saving power and conserving dynamic range.
The technique proposed by the '910 patent, while suitable for many ADC applications, is limited by the resolution of the back-end of the ADC. This limitation is also shared by other conventional calibration techniques, in that they require the back-end pipeline to be as accurate as the calibration accuracy. Specifically, each stage in the back-end has a finite resolution, characterized by the number of bits that are available for processing the input. For example, if the output of the first stage is to be calibrated to 14-bit accuracy, then the back-end pipeline needs to be 14-bit accurate when processing the dither. The back-end is used to digitize the dither, which in turn is used to estimate the gain. Since the dither signal is smaller than the full-scale (FS) input signal, more bits are required in the back-end to achieve the same effective resolution. When processing an FS input, more bits are used and therefore the effective resolution is higher than when a small signal, such as the dither signal, is applied. For example, if the magnitude of the dither signal is ¼th the magnitude of the full scale signal, then for the dither signal to be digitized with a 14-bit accuracy, it will require a 16-bit back-end digitizer. If the accuracy of the back-end is not sufficient to handle the dither, there could be an error in estimating the dither error, which in turn results in an estimation error for the ADC output.
The traditional solution to this problem is to simply add more resolution, increasing the accuracy of the back-end. However, the additional hardware involved consumes extra power and incurs performance overhead. It is necessary to calibrate several stages (starting from the back-end) to ensure the overall accuracy of the ADC. Even then, the accuracy may still be inadequate because the dither may be too small compared to the input signal. This requires calibrating the back-end to an even higher accuracy. In some cases, it may not be possible to achieve the desired accuracy without adding additional stages to increase the overall pipeline accuracy.